Timing closure

Timing closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.

The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.

Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. Design Compiler by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.

A timing requirement needs to be translated into a static timing constraint for an EDA tool to be able to handle it.

Copyright (c) 2007 Alessandro Uber.
Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License".
Content is covered by disclaimers.